• / 8
  • 下载费用:10 金币  

基于BASYS2的简易数字钟.doc

关 键 词:
基于BASYS2的简易数字钟.doc
资源描述:
/***********************************verilog*************************************/module clock_final(clk,clr,switch,ad,adj,o_seg,a);input clk,clr,switch,ad;input [3:0]adj;// output [2:0]led;//led 灯output [6:0]o_seg;//7 段数码管output [3:0]a; //扫描输出reg [6:0]segs;//数码管寄存器reg [3:0]a;reg [15:0] temp;//显示过程的中间变量wire [23:0] cnt;//走时模式和校时模式临时变量wire en0,enp1,enp2,enp3,enp4,enp5,cp1hz,cp,out_500hz;//switch - N3 转换信号 分两个屏一个是小时/ 分钟,一个是分钟/秒//clr - E2 清零信号//adj[3]控制小时的十位设置//adj[2]控制小时的个位设置//adj[1]控制分钟的十位设置//adj[0]控制分钟的个位设置initial begina=4'b1110;end //初始化assign cp=cp1hz,//判断 ad 是否等于 1,如果等于,cp 就输出 cp10hz 否则就输出cp1hz,en0=(~ad)|(switchin50MHz_out1Hz u0(clk,cp1hz);//输出频率 1HZin50MHz_out_8MHz u7(clk,out_500hz);//输出 500HZcounter10 u1(en0,clr,cp,cnt[3:0]); //second 个位计数counter6 u2(enp1,clr,cp,cnt[7:4]);//second 十位计数counter10 u3(enp2,clr,cp,cnt[11:8]);//minutes 个位计数counter6 u4(enp3,clr,cp,cnt[15:12]);//minutes 十位计数counter10_h u5(enp4,clr,cp,cnt[19:16],cnt[23:20]);//hours 个位计数counter3 u6(enp5,clr,cp,cnt[23:20]); //hours 十位计数// //// always@(ad ) begin //显示模式选择// if((~ad)) begin temp[15:0]=cnt1[15:0];temp[31:16]=cnt1[23:8];end// else begin temp[15:0]=cnt;temp[31:16]=cnt[23:8];end// endalways@(posedge clk)begin if(switch==1'b0)temp=cnt[23:8];else if(switch==1'b1)temp=cnt[15:0];endalways@(posedge out_500hz)beginif(a==4'b1110) a=4'b1101;//M13else if(a==4'b1101) a=4'b1011;//J12else if(a==4'b1011) a=4'b0111;//F12else a=4'b1110;//K14endalways@(posedge clk) //数码管显示译码if(switch==1'b0)beginif(a==4'b1110)//K14 begin case(temp[3:0])4'd0: segs = 7'b1000000;//04'd1: segs = 7'b1111001;//14'd2: segs = 7'b0100100;4'd3: segs = 7'b0110000;4'd4: segs = 7'b0011001;4'd5: segs = 7'b0010010;4'd6: segs = 7'b0000010;4'd7: segs = 7'b1111000;4'd8: segs = 7'b0000000;4'd9: segs = 7'b0010000;//9default segs = 7'b1111111;endcaseendelse if(a==4'b1101)//M13begin case(temp[7:4])4'd0: segs = 7'b1000000;4'd1: segs = 7'b1111001;4'd2: segs = 7'b0100100;4'd3: segs = 7'b0110000;4'd4: segs = 7'b0011001;4'd5: segs = 7'b0010010;default segs = 7'b1111111;endcaseendelse if(a==4'b1011)begincase(temp[11:8])//hours 个位4'h0: segs = 7'b1000000;4'h1: segs = 7'b1111001;4'h2: segs = 7'b0100100;4'h3: segs = 7'b0110000;4'h4: segs = 7'b0011001;4'h5: segs = 7'b0010010;4'h6: segs = 7'b0000010;4'h7: segs = 7'b1111000;4'h8: segs = 7'b0000000;4'h9: segs = 7'b0010000;4'ha: segs = 7'b0001000;default segs = 7'b1111111;endcaseendelse if(a==4'b0111)begin case(temp[15:12])//hours 十位4'h0: segs = 7'b1000000;4'h1: segs = 7'b1111001;4'h2: segs = 7'b0100100;default segs = 7'b1111111;endcaseendendelse if(switch==1)begin if(a==4'b1110)begincase(temp[3:0])4'd0: segs = 7'b1000000;4'd1: segs = 7'b1111001;4'd2: segs = 7'b0100100;4'd3: segs = 7'b0110000;4'd4: segs = 7'b0011001;4'd5: segs = 7'b0010010;4'd6: segs = 7'b0000010;4'd7: segs = 7'b1111000;4'd8: segs = 7'b0000000;4'd9: segs = 7'b0010000;default segs = 7'b1111111;endcaseendelse if(a==4'b1101)begincase(temp[7:4])4'd0: segs = 7'b1000000;4'd1: segs = 7'b1111001;4'd2: segs = 7'b0100100;4'd3: segs = 7'b0110000;4'd4: segs = 7'b0011001;4'd5: segs = 7'b0010010;// 4'd6: segs = 7'b0000010;// 4'd7: segs = 7'b1111000;// 4'd8: segs = 7'b0000000;// 4'd9: segs = 7'b0010000;default segs = 7'b1111111;endcaseendelse if(a==4'b1011)begincase(temp[11:8])4'd0: segs = 7'b1000000;4'd1: segs = 7'b1111001;4'd2: segs = 7'b0100100;4'd3: segs = 7'b0110000;4'd4: segs = 7'b0011001;4'd5: segs = 7'b0010010;4'd6: segs = 7'b0000010;4'd7: segs = 7'b1111000;4'd8: segs = 7'b0000000;4'd9: segs = 7'b0010000;default segs = 7'b1111111;endcaseendelse if(a==4'b0111)begincase(temp[15:12])4'd0: segs = 7'b1000000;4'd1: segs = 7'b1111001;4'd2: segs = 7'b0100100;4'd3: segs = 7'b0110000;4'd4: segs = 7'b0011001;4'd5: segs = 7'b0010010;default segs = 7'b1111111;endcase endendendmodule/***************分频模块***********************************************///分频模块 1Hzmodule in50MHz_out1Hz(in_50MHz,out_1Hz); input in_50MHz; output out_1Hz; reg out_1Hz; reg [31:0]cnt; //use cnt to count always@(posedge in_50MHz) begin if(cnt 32'd24999999)//计数到 24999999begin cnt = cnt + 1'B1;end else begin cnt = 32'b0; out_1Hz = ~out_1Hz; //频率为 1HZendendendmodulemodule in50MHz_out_8MHz(in_50MHz,out_500hz); input in_50MHz; output out_500hz; reg out_500hz; reg [31:0]cnt; //use cnt to count always@(posedge in_50MHz) begin if(cnt 32'd50000)//begin cnt = cnt + 1'B1;end else begin cnt = 32'b0; out_500hz = ~out_500hz; //频率为 1HZendendendmodule// counter10(0~9) module counter10(en,clr,clk,q);input en,clr,clk;output [3:0] q;reg [3:0] q;always@(posedge clk)beginif(clr) q=4'd0;//clr=0 时,清零else if(~en) q=q;// EN=0,暂停计数else if (q==4'b1001) q=4'b0000; else q=q+1;//计数器加 1endendmodule//counter10(时针个位)module counter10_h(en,clr,clk,q,p);input en,clr,clk;input [3:0]p;output [3:0] q;reg [3:0] q;always@(posedge clk)beginif(clr) q=4'd0;//clr=0 时,清零else if(~en) q=q;// EN=0,暂停计数else if(p==4'b0010else if ((q==4'b1001) else q=q+1;//计数器加 1endendmodule/*****************计数模块 ********************************************/// counter6.v(0~5)module counter6(en,clr,clk,q);input en,clr,clk;output [3:0] q;reg [3:0] q;always@(posedge clk)beginif(clr) q=4'b0000;//clr=0,清零else if(~en) q=q;//EN=0,暂停计数else if(q==4'b0101) q=4'b0000;else q=q+1'b1;//计数器增 1endendmodule//counter3(0~2)module counter3(en,ncr,clk,q);input en,ncr,clk;output [3:0] q;reg [3:0] q;always@(posedge clk)beginif(ncr) q=4'b0000;//NCR=0,同步清零else if(en==0) q=q;//EN=0,暂停计数else if(q==4'd2) q=4'b0000;else q=q+1'b1;//计数器增 1endEndmodule/***********************************ucf***************************************/NET “clk“ LOC = B8 | IOSTANDARD = “LVCMOS33“;NET “ad“ LOC = G12 | IOSTANDARD = “LVCMOS33“;NET “switch“ LOC = N3 | IOSTANDARD = “LVCMOS33“;NET “clr“ LOC = E2 | IOSTANDARD = “LVCMOS33“;NET “adj[0]“ LOC = P11 | IOSTANDARD = “LVCMOS33“;NET “adj[1]“ LOC = L3 | IOSTANDARD = “LVCMOS33“;NET “adj[2]“ LOC = K3 | IOSTANDARD = “LVCMOS33“;NET “adj[3]“ LOC = B4 | IOSTANDARD = “LVCMOS33“;NET “o_seg[0]“ LOC = L14 | IOSTANDARD = “LVCMOS33“;NET “o_seg[1]“ LOC = H12 | IOSTANDARD = “LVCMOS33“;NET “o_seg[2]“ LOC = N14 | IOSTANDARD = “LVCMOS33“;NET “o_seg[3]“ LOC = N11 | IOSTANDARD = “LVCMOS33“;NET “o_seg[4]“ LOC = P12 | IOSTANDARD = “LVCMOS33“;NET “o_seg[5]“ LOC = L13 | IOSTANDARD = “LVCMOS33“;NET “o_seg[6]“ LOC = M12 | IOSTANDARD = “LVCMOS33“;NET “a[3]“ LOC = K14 | IOSTANDARD = “LVCMOS33“;NET “a[2]“ LOC = M13 | IOSTANDARD = “LVCMOS33“;NET “a[1]“ LOC = J12 | IOSTANDARD = “LVCMOS33“;NET “a[0]“ LOC = F12 | IOSTANDARD = “LVCMOS33“;
展开阅读全文
  微传网所有资源均是用户自行上传分享,仅供网友学习交流,未经上传用户书面授权,请勿作他用。
0条评论

还可以输入200字符

暂无评论,赶快抢占沙发吧。

关于本文
本文标题:基于BASYS2的简易数字钟.doc
链接地址:https://www.weizhuannet.com/p-8127618.html
微传网是一个办公文档、学习资料下载的在线文档分享平台!

网站资源均来自网络,如有侵权,请联系客服删除!

 网站客服QQ:80879498  会员QQ群:727456886

copyright@ 2018-2028 微传网络工作室版权所有

     经营许可证编号:冀ICP备18006529号-1 ,公安局备案号:13028102000124

收起
展开