FPGA通用N倍奇数分频.doc

1、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;-ENTITY DIV_N ISGENERIC(N:INTEGER:=3);PORT(CLK,CLR:IN STD_LOGIC;CLK_OUT:OUT STD_LOGIC);END;-ARCHITECTURE ONE OF DIV_N ISSIGNAL COUNT1,COUNT2:INTEGER;SIGNAL CLK_REG1,CLK_REG2:STD_LOGIC;BEGINONE: PROCESS(CLK,CLR)BEGINIF CLR=1 THENCOUNT1=0;CLK_REG1=0;ELSIF CLKEV

2、ENT AND CLK=1 THENIF COUNT1=N-1 THEN COUNT1=0;CLK_REG1=NOT CLK_REG1;ELSIF COUNT1=(N-1)/2 THENCOUNT1=COUNT1+1;CLK_REG1=NOT CLK_REG1;ELSE COUNT1=COUNT1+1;END IF;END IF;END PROCESS;-TWO: PROCESS(CLK,CLR)BEGINIF CLR=1 THENCOUNT2=0;CLK_REG2=0;ELSIF CLKEVENT AND CLK=0 THENIF COUNT2=N-1 THEN COUNT2=0;CLK_REG2=NOT CLK_REG2;ELSIF COUNT2=(N-1)/2 THENCOUNT2=COUNT2+1;CLK_REG2=NOT CLK_REG2;ELSE COUNT2=COUNT2+1;END IF;END IF;END PROCESS;-CLK_OUT= CLK_REG1 OR CLK_REG2;END;